A project proposal submitted by Burç Mısırlıoğlu, faculty member of Sabancı University Faculty of Engineering and Natural Sciences, is entitled to receive support within the framework of the TÜBİTAK 1001 Scientific and Technological Research Support Program.
Burç Mısırlıoğlu’s project is entitled “Negative capacitance stability and limits in structures with ferroelectric/dielectric layers”. Kürşat Şendur and Murat Kaya Yapıcı from Sabancı University Faculty of Engineering and Natural Sciences and Barış Okatan from İzmir Institute of Technology are involved in the project as researchers. The project aims to research the feasibility and stability of negative capacitance behavior, which is estimated to save power in semiconductor-based transistors via use of multi-layered ferroelectric/dielectric structures.
Regarding the importance of the project, Mısırlıoğlu emphasized the following: Decreasing the power consumption of integrated circuits is an effort that goes simultaneously with the effort to decrease the size of devices. These circuits are usually based on MOSFETs (Metal oxide semiconductor field effect transistors). MOSFETs are such small devices that they can now only be observed with electron microscopes. For example, there may be billions of MOSFETs located in an area not larger than 1-2 square centimeters on a processor, which is considered to be one of the foremost examples of nanotechnology. On the other hand, these and similar devices are responsible for approximately 10% of global electricity consumption. There are scenarios in which this share may go as high as 50% in 10 years’ time. Therefore, it is essential that they be able to work on low levels of power. MOSFET devices can be basically considered as electricity switches that go “on” and “off” millions of times in a second, and as one might guess, when they are “on”, an electrical current can go through the device, and when “off”, no electrical current can go through; in other words, there are low resistance and high resistance states. In fact, whether an electrical current goes through or not corresponds to “1” and “0” in informatics language. There have been efforts for years to integrate ferroelectric materials into MOSFETs to implement memory function and the “negative capacitance” effect entered the agenda of the semiconductor industry as a "side effect". Designing MOSFETs with low power consumption through this “effect” has been a popular area of research. In this project, we aim to examine theoretically whether or not negative capacitance in a MOSFET device setting is a stable intrinsic property using some selected ferroelectric-dielectric nano-layered materials, and to understand the physics of this behavior in depth as well as its dependence on material parameters. We also hope to be able to come up with some device proposal at the end of the project.